Amlogic S905L is a New Cheap SoC from Amlogic

atb_team September 20, 2016

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Most of you know that in the market there are a lot of SoC (System on Chip) from Amlogic. The most popular chip, which could be found in TV boxes is Amlogic S905. Recently expanded range of devices for the TV boxes equipped with Amlogic S905X. Amlogic company decided to give manufacturers TV Boxes, cheaper solution based on the chipset S905X called Amlogic S905L. New Amlogic S905L will appear soon in the new TV boxes, and will be slim with several features, among others: without VP9 codec, camera interface, nor TS inputs.

Amlogic S905L specifications (based on S905L Quick Referent Manual):

CPU – Quad core ARM Cortex-A53 CPU up to 2GHz (DVFS) with Neon and Crypto extensions, unified L2 cache
3D GPU – Penta-core ARM Mali-450 GPU up to 750 MHz+ (DVFS)
2.5D GPU – Fast bitblt engine with dual inputs and single output, programmable raster operations (ROP) and polyphase scaling filter, etc..
Crypto Engine – AES/AES-XTS block cipher with 128/192/256 bits keys, DES/TDES block cipher, built-in hardware True Random Number Generator (TRNG), CRC and SHA-1/SHA-2/HMAC SHA engine
Video/Picture CODEC
- Amlogic Video Engine (AVE) with dedicated hardware decoders and encoders
- Supports multiple “secured” video decoding sessions and simultaneous decoding and encoding
- Video/Picture Decoding
  - H.265 HEVC [email protected] up to [email protected]
  - H.264 AVC [email protected] up to [email protected]
  - H.264 MVC up to 1080p @60fps
  - MPEG-4 [email protected] up to [email protected] (ISO-14496)
  - WMV/VC-1 SP/MP/AP up to [email protected]
  - AVS-P16(AVS+) /AVS-P2 JiZhun Profile up to [email protected]
  - MPEG-2 MP/HL up to [email protected] (ISO-13818)
  - MPEG-1 MP/HL up to [email protected] (ISO-11172)
  - RealVideo 8/9/10 up to [email protected]
  - WebM up to VGA
  - MJPEG and JPEG unlimited pixel resolution decoding (ISO/IEC-10918)
  - Supports JPEG thumbnail, scaling, rotation and transition effects
- Video/Picture Encoding
  - Independent JPEG and H.264 encoder with configurable performance/bit-rate
  - JPEG image encoding
  - H.264 video encoding up to [email protected] with low latency
Video Post-Processing Engine – HDR10 & HLG HDR processing, motion adaptive 3D noise reduction filter, advanced motion adaptive edge enhancing de-interlacing engine, 3:2 pull-down support, deblocking fliters, etc..
Video Output
- Built-in HDMI 2.0b transmitter including both controller and PHY with CEC, HDR and HDCP 2.2, [email protected] max resolution output
- CVBS 480i/576i standard definition output
Audio Decoder and Input/Output
- Supports MP3, AAC, WMA, RM, FLAC, Ogg and programmable with 7.1/5.1 down-mixing
- I2S audio interface supporting 8-channel (7.1) input and output
- Built-in serial digital audio SPDIF/IEC958 output and PCM input/output
- Built-in stereo audio DAC
- Stereo digital microphone PDM input
- Supports concurrent dual audio stereo channel output with combination of Analog+PCM or I2S+PCM
Memory and Storage Interface
- 16/32-bit SDRAM memory interface running up to DDR2133
- Supports up to 2GB DDR3/4, DDR3L, LPDDR2, LPDDR3 with dual ranks
- Supports SLC/MLC/TLC NAND Flash with 60-bit ECC
- SDSC/SDHC/SDXC card and SDIO interface with 1-bit and 4-bit data bus width supporting up to UHS-I SDR104
- eMMC and MMC card interface with 1/4/8-bit data bus width fully supporting spec version 5.0 HS400
- Supports serial 1, 2 or 4-bit NOR Flash via SPI interface
- Built-in 4k bits One-Time-Programming memory for key storage
Network
- Integrated 10/100M MAC controller with 10/100M PHY interface
- Supports Energy Efficiency Ethernet (EEE) mode
Integrated I/O Controllers and Interfaces
- Dual USB 2.0 high-speed USB I/O, one USB Host and one USB OTG
- Multiple UART, I2C and SPI interface with slave select
- Multiple PWMs
- Programmable IR remote input/output controllers
- Built-in 10bit SAR ADC with 2 input channels
- General Purpose IOs with built-in pull up and pull down
System, Peripherals and Misc. Interfaces
- Integrated general purpose timers, counters, DMA controllers
- 24 MHz crystal input
- Embedded debug interface using ICE/JTAG
Power Management
- Multiple external power domains controlled by PMIC, and internal ones controlled by software
- Multiple sleep modes for CPU, system, DRAM, etc.
- Multiple internal PLLs for DVFS operation
- Multi-voltage I/O design for 1.8V and 3.3V
- Power management auxiliary processor in a dedicated always-on (AO) power domain that can communicate with an external PMIC
Security
- Trustzone based Trusted Execution Environment (TEE)
- Secured boot, encrypted OTP, encrypted DRAM with memory integrity checker, hardware key ladder and internal control buses and storage
- Protected memory regions and electric fence data partition
- Hardware based Trusted Video Path (TVP) , video watermarking and secured contents (needs SecureOS software)
- Secured IO and secured clock
Package – LFBGA,13x13mm, 20×20 ball matrix, 0.65 ball pitch, RoHS compliant